1. Field of the Invention
The present invention relates to a circuit structure of an internal input/output (I/O) buffer achieving a high-precision timing verification test of a semiconductor device (hereinafter referred to as an xe2x80x9cLSIxe2x80x9d).
2. Description of the Background Art
FIG. 23 shows a structure of a conventional LSI with a semiconductor test device (hereinafter referred to as a xe2x80x9cLSI testerxe2x80x9d) in the test state.
An LSI tester 500 is composed of a tester body 504 and a test head 506. The tester body 504 includes a timing generator 501 generating a timing signal necessary as a condition of the LSI test, a waveform formatter 502 determining a waveform of rising or falling timing, and a power-supply/DC measuring unit 503 having a power supply for driving a device, a measuring portion for the DC of the device, and the like. The test head 506 makes direct transmissions of a signal to/from an LSI to be test 505 on the basis of a control signal obtained from the test body 504 through a cable 507.
In testing the LSI to be test 505, a pin electronic tester driver 509 stored in the test head 506 generates a test signal that is applied through a POGO pin 510, a wire 512 of a DUT board 511, an electrode 514 of a socket 513, and a wire 516 of an LSI package 515 to the LSI to be test 505. Conversely, after the operation of the LSI 505, a reaction signal is transmitted along the same path to a tester comparator 517 in the LSI tester 500, in which that signal is compared with an expected value EXP, by which the LSI tester 500 judges whether the LSI 505 operates as designed or not.
In testing the LSI 505 by the LSI tester 500 as described above, one of test items, the timing verification test, has caused a problem as described below. As the LSI 505 increases its operating speed, an interface thereof requires a clock speed of several hundreds MHz, which considerably reduces the value of setup or hold timing that is a product spec of the LSI 505. This makes it difficult for the LSI tester 500 to perform a high-precision timing verification test with rigid timing conditions.
To give a concrete example, we refer to FIGS. 24 and 25 that show a structure of a conventional I/O buffer cell 520, and a timing relation between a data terminal 521 and a clock terminal 522 in the timing verification test, respectively.
As shown in FIG. 24, a clock CLK obtained from the clock terminal 522 is applied through a clock input portion 611 to respective control inputs of a driver 524 and a receiver 525. The operation of the driver 524 and the receiver 525 is controlled by the clock CLK.
Further, data DATA obtained from the data terminal 521 is applied through a data input/output portion 612 to one input of the receiver 525, and a reference voltage VREF is applied through a reference-voltage input portion 607 to the other input of the receiver 25. The receiver 525 compares the data DATA and the reference voltage VREF, and according to the comparison result, outputs an internal signal obtained through buffering, via a signal output portion 610 to an internal logic 523.
The output of the internal logic 523 is applied through a signal input portion 609 to an input of the driver 524, the output of which is applied through the data input/output portion 612 to the data terminal 521.
If a product standard of the setup time of the data DATA relative to the clock CLK 5 of the I/O buffer cell 520 provided in the LSI to be test 505 is 0.2 ns, for example, consider the case where the LSI tester 500 performs the timing verification test of whether the I/O buffer cell 520 in the LSI to be test 505 satisfies the timing condition that the setup time be 0.2 ns.
Even in the timing verification test with a setup time TS1 in FIG. 25 where L1 depicts a waveform for the data DATA and L3 a waveform for the clock CLK, the skew xcex1 occurs in actual practice to both of the data DATA and the clock CLK. If the data DATA gains phase lead as depicted by a waveform L2 and the clock CLK gains phase lag as depicted by a waveform L4, the timing verification test will be performed with a setup time ts2 which is considerably longer than the original setup time TS1.
To be concrete, assuming that signal propagation time variations due to the timing skew of the signals caused by the LSI tester 500 are xc2x10.15 ns, those due to the lengths of the wire 512 of the DUT board 511 and the electrode 413 of the socket 513 are xc2x10.05 ns, and those due to the length of the wire 516 of the package 515 are xc2x10.1 ns, a phase difference between the clock CLK and the data DATA reaches 0.6 ns maximum.
Thus, when the clock CLK gains phase lag of 0.6 ns with respect to the data DATA, in order to surely ensure the setup time of 0.2 ns, a test program value tp is required to be set at xe2x88x920.4 ns (so as to advance the clock CLK 0.4 ns faster than the data DATA). The reason for setting the value at xe2x88x920.4 ns is as follows: If the test program value tp is set larger than xe2x88x920.4 ns, when the clock CLK gains phase lag of 0.6 ns with respect to the data DATA, the timing verification test will be performed with the setup time of (tp+0.6) ns which is larger than 0.2 ns. This incurs the risk that the LSI to be test 505 may be wrongly judged as acceptable even if failing to satisfy the setup time of 0.2 ns.
The timing skew in the LSI tester 500, however, still remains even though the test program value tp is set at xe2x88x920.4 ns. Thus, when timing of the actual application of the signals to the LSI 505 is the worst (the data DATA gains a phase lag of 0.6 ns with respect to the clock CLK), the timing skew of xe2x88x921.0 ns may occur.
When the timing of the application is the worst as described above, most of acceptable LSIs to be test 505 will be judged as defective, which causes extreme reduction in yield of the LSI 505.
A first aspect of the present invention is directed to a semiconductor device comprising a first input/output buffer cell receiving first and second input signals and a first test-mode signal and buffering the first input signal to output an internal signal. The first input/output buffer cell comprises: delay means for receiving the first input signal and delaying the first input signal for a predetermined delay time to output a first delay input signal; first input-signal selecting means for outputting either of the first delay input signal and the second input signal as a first selection signal on the basis of the first test-mode signal; and internal-signal output means for buffering the first input signal to output the internal signal, the operation of the internal-signal output means controlled by the first selection signal.
Preferably, according to a second aspect of the present invention, the semiconductor device of the first aspect further comprises: a second input/output buffer cell for buffering the internal signal to output an output signal to the outside. The operation of the second input/output buffer cell is controlled by the second input signal.
Preferably, according to a third aspect of the present invention, the semiconductor device of the second aspect further comprises: an internal-signal processing circuit for processing the internal signal in a predetermined way to output a processed signal; and signal control means for receiving a second test-mode signal and controlling the validity or invalidity of outputting the processed signal to the first and the second input/output buffer cells on the basis of the second test-mode signal.
Preferably, according to a fourth aspect of the present invention, the semiconductor device of the first aspect further comprises: an internal-signal processing circuit for processing the internal signal in a predetermined way to output a processed signal; second input-signal selecting means for receiving a second test-mode signal and outputting either of the processed signal and the internal signal as a second selection signal on the basis of the second test-mode signal; and a second input/output buffer cell for buffering the second selection signal to output an output signal to the outside. The operation of the second input/output buffer cell is controlled by the second input signal.
Preferably, according to a fifth aspect of the present invention, in the semiconductor device of the first aspect, the delay means comprises: an inverter chain comprising a plurality of series-connected inverters with its first-stage inverter receiving the first input signal at its input; inverter delay-time control means for controlling respective signal propagation delay times of the plurality of inverters; and a selector for selectively outputting a signal related to one of the outputs of the plurality of inverters as the first delay input signal.
Preferably, according to a sixth aspect, in the semiconductor device of the fifth aspect, the plurality of inverters includes an odd number, not less than three, of inverters in loop connection with the output of its last-stage inverter connected to the input of its first-stage inverter. The inverter delay-time control means includes: signal comparison means for comparing the number of reference oscillations and the number of oscillations of an oscillating signal obtained by oscillating the odd number of inverters in loop connection during a predetermined period of time, to output its comparison result; and control-signal output means for determining the signal propagation delay time on the basis of the comparison result, and applying a control signal indicating the signal propagation delay time to the plurality of inverters.
Preferably, according to a seventh aspect of the present invention, in the semiconductor device of the sixth aspect, a total signal propagation delay time of the plurality of inverters is set to be the same as a cycle of the first input signal.
An eighth aspect of the present invention is directed to a test board for testing a semiconductor device. The semiconductor device includes at least first and second input terminals and an input/output buffer cell for buffering a signal obtained from the first input terminal to output an internal signal. The operation of the semiconductor device is controlled by a signal obtained from the second input terminal. The test board comprises: first delay means for delaying a signal to be transmitted therethrough for a first signal propagation delay time; second delay means for delaying a signal to be transmitted therethrough for a second signal propagation delay time different from the first signal propagation delay time; and signal-transmission-path forming means for receiving a first test signal and forming, in a first test mode, a first signal transmission path along which the first test signal is transmitted through the first delay means to the first input terminal of the semiconductor device, and a second transmission path along which the first test signal is transmitted through the second delay means to the second input terminal of the semiconductor device.
Preferably, according to a ninth aspect of the present invention, in the test board of the eighth aspect, the second signal propagation delay time is set longer than the first signal propagation delay time. The test board further comprises: third delay means for delaying a signal to be transmitted therethrough for a third signal propagation delay time; and fourth delay means for delaying a signal to be transmitted therethrough for a fourth signal propagation delay time shorter than the third signal propagation delay time. Further, in a second test mode, the signal-transmission-path forming means receives a second test signal and forms a third signal transmission path along which the second test signal is transmitted through the third delay means to the first input terminal of the semiconductor device, and a fourth signal transmission path along which the second test signal is transmitted through the fourth delay means to the second input terminal of the semiconductor device.
Preferably, according to a tenth aspect of the present invention, the semiconductor device in the test board of the eighth aspect further includes an output terminal capable of outputting a signal obtained from the first input terminal at a setting of a predetermined condition, without logically processing the signal. The test board further comprises: third delay means for delaying a signal to be transmitted therethrough for a third signal propagation delay time; fourth delay means for delaying a signal to be transmitted therethrough for a fourth signal propagation delay time equal to the third signal propagation delay time; and tolerable-output-time delay means for delaying a signal to be transmitted therethrough for a predetermined tolerable output time. The signal-transmission-path forming means further receives a second test signal. In a first mode for testing an output time, the signal-transmission-path forming means forms a first signal transmission path for testing an output time, capable of outputting a signal obtained by transmitting the second test signal through the fourth delay means and the tolerable-output-time delay means, to the outside as a first comparison signal. In a second mode for testing an output time, the signal-transmission-path forming means forms second and third signal propagation paths for testing an output time, along which the first and the second test signals are transmitted through the third and the fourth delay means to the first and the second input terminals, respectively, and a fourth signal transmission path for testing an output time, capable of outputting a signal obtained from the output terminal to the outside as a second comparison signal.
Preferably, according to an eleventh aspect of the present invention, in the first test mode, the signal-propagation-path forming means in the test board of the eighth aspect terminates the first and the second input terminals via first and second terminating resistors, respectively.
Preferably, according to a twelfth aspect of the present invention, the second input terminal in the test board of the eighth aspect includes first and second differential input terminals. Further, the operation of the semiconductor device is controlled by a signal obtained from the first and the second differential input terminals. Further, in the first test mode, the signal-transmission-path forming means applies the first test signal through the second delay means to the first differential input terminal of the second input terminal of the semiconductor device, and applies a fixed voltage to the second differential input terminal.
Preferably, according to a thirteenth aspect of the present invention, in the first test mode, the signal-transmission-path forming means in the test board of the twelfth aspect terminates the first input terminal via a first terminating resistor, and connects the first and the second differential input terminals with a resistance element.
Preferably, according to a fourteenth aspect of the present invention, the first and the second signal transmission paths in the test board of the eighth aspect are formed in such a manner that a transmission path of the first test signal branches into two with a magnetic relay, an MOS transistor, or a power splitter.
Preferably, according to a fifteenth aspect of the present invention, the first and the second delay means in the test board of the eighth aspect are formed of an axial cable determining a delay time according to its length, or an active delay element capable of setting a delay time through a predetermined setting operation.
In the semiconductor device of the first aspect, the input/output buffer cell comprises delay means for delaying the first input signal for a predetermined delay time to output the first delay input signal; first input-signal selecting means for outputting either of the first delay input signal and the second input signal as the first selection signal on the basis of the first test-mode signal; and internal-signal output means for buffering the first input signal to output the internal signal, the operation of the internal-signal output means controlled by the first selection signal.
Thus, in the test state where the first test-mode signal indicating to select the first delay input signal and a signal for test as the first input signal are applied to the first input/output buffer cell, the internal-signal output means is controlled by the first delay input signal which is obtained by delaying the first input signal for a predetermined period of time and buffers the first input signal to output the internal signal.
As a result, only with the application of the signal for test as the first input signal, the setup-time verification test with the aforementioned delay time defined as the setup time can be performed, irrespective of the timing skew of the first input signal to be caused when a tester or the like outputs the first input signal.
The semiconductor device of the second aspect further comprises the second input/output buffer cell for buffering the internal signal to output the output signal to the outside. Thus, in the aforementioned test state, the internal signal can be monitored from the outside as the output signal.
The semiconductor device of the third aspect further comprises the signal control means for controlling the validity or invalidity of outputting the processed signal to the first and the second input/output buffer cells on the basis of the second test-mode signal. Thus, if the second test-mode signal indicating the invalidity of outputting the processed signal to the first and the second input/output buffer cells is applied to the signal control means in the aforementioned test state, the semiconductor device cannot be easily affected by the internal-signal processing circuit.
The semiconductor device of the fourth aspect further comprises the second input-signal selecting means for outputting either of the processed signal and the internal signal as the second selection signal on the basis of the second test-mode signal; and the second input/output buffer cell for buffering the second selection signal to output the output signal to the outside, the operation of the second input/output buffer cell controlled by the second input signal.
If the second test-mode signal indicating to select the internal signal is applied to the second input-signal selecting means in the aforementioned test state, the internal signal can be monitored from the outside as the output signal.
Further, if the second test-mode signal indicating to select the processed signal is applied to the second signal selecting means in normal operation, the processed signal can be outputted as the output signal to the outside. This minimizes the number of output terminals for outputting the processed signal and the internal signal to the outside.
In the semiconductor device of the fifth aspect, the delay means comprises the inverter delay-time control means for controlling the respective signal propagation delay times of the plurality of inverters; and the selector for selectively outputting a signal related to one of the outputs of the plurality of inverters as the first delay input signal.
Thus, a relatively small change of the predetermined delay time is made under the control of the inverter-delay-time control means, and a relatively great change thereof is made through the selection by the selector.
The semiconductor device of the sixth aspect has the comparison means compare the number of reference oscillations and the number of oscillations of the oscillating signal obtained by oscillating the odd number of inverters during a predetermined period, to output the comparison result, and the device also has the control-signal output means determine the aforementioned signal propagation delay time on the basis of the comparison result.
Thus, the predetermined delay time can be accurately set on the basis of the predetermined period of time and the number of reference oscillations.
In the semiconductor device of the seventh aspect, the total signal-propagation delay time of the plurality of inverters is set to be the same as the cycle of the first input signal.
Thus, for the predetermined delay time of not less than the half cycle of the first input signal, the first input signal substantially gains phase lead of {(first input signal cycle)xe2x88x92(predetermined delay time)}.
As a result, only with the application of the signal for test as the first input signal to the first input/output buffer cell, the hold-time verification test with the aforementioned phase lead {(first input signal cycle)xe2x88x92(predetermined delay time)} defined as the hold time can be performed, irrespective of the timing skew of the first input signal to be caused when the tester or the like outputs the first input signal.
In the test board of the eighth aspect, the signal-transmission-path forming means, in the first mode, forms the first signal transmission path along which the first test signal is transmitted through the first delay means to the first input terminal of the semiconductor device; and the second signal transmission path along which the first test signal is transmitted through the second delay means to the second input terminal of the semiconductor device.
Thus, the timing verification test can be performed by applying the signals defining a time difference between the first and the second signal propagation delay times as the setup time or the hold time to the first and the second input terminals. At this time, the test is not affected by the timing skew of the first test signal to be caused when the tester or the like outputs the first test signal. Thus, the high-precision timing verification test can be performed.
In the test board of the ninth aspect, the signal-transmission-path forming means, in the second mode, forms the third signal transmission path along which the second test signal is transmitted through the third delay means to the first input terminal of the semiconductor deceive; and the fourth signal transmission path along which the second test signal is transmitted through the fourth delay means to the second input terminal of the semiconductor device.
The second signal propagation delay time is set longer than the first signal propagation delay time, and the fourth signal propagation delay time is set longer than the third signal propagation delay time.
Thus, the timing verification test in the first test mode can be performed with the time difference between the first and the second signal propagation delay times defined as the setup time, while the timing verification test in the second test mode can be performed with the time different between the first and the second signal propagation delay times defined as the hold time.
Further, if the first and the second test signals in the first test mode are different from those in the second test mode, it becomes possible to disperse the load on the tester or the like for outputting the first and the second test signals.
In the test board of the tenth aspect, the signal-transmission-path forming means, in the first mode for testing an output time, forms the first signal transmission path for testing an output time, capable of outputting the signal obtained by transmitting the second test signal through the fourth delay means and the tolerance output time delay means, to the outside as the first comparison signal. Further, in the second mode for testing an output time, the signal-transmission-path forming means forms the second and the third signal transmission paths for testing an output time, along which the first and the second test signals are transmitted through the third and the fourth delay means to the first and the second input terminals, respectively, and the fourth transmission path for testing an output time, capable of outputting the signal obtained from the output terminal to the outside as the second comparison signal.
Thus, whether the output time of the semiconductor device is within the tolerable output time or not can be judged by sequentially setting the first and the second modes for testing an output time and comparing the time when the change of the second test signal appears in the first comparison signal and the time when the change of the second test signal appears in the second comparison signal.
In the test board of the eleventh aspect, the signal-transmission-path forming means, in the first test mode, terminates the first and second input terminals via the first and the second terminating resistors, respectively. This prevents the occurrence of reflected noise of the signal applied to the first and the second input terminals.
In the test board of the twelfth aspect, the signal-transmission-path forming means, in the first test mode, connects the first test signal through the second delay means to the first differential input terminal of the second input terminal of the semiconductor device, and applies the fixed voltage to the second differential input terminal. This eliminates the skew of the signal applied to the second differential input terminal, thereby achieving a high-precision timing verification test.
In the test board of the thirteenth aspect, the signal-transmission-path forming means, in the first test mode, terminates the first input terminal via the first terminating register, and connects the first and the second differential input terminals with the resistance element. This prevents the occurrence of reflected noise of the signal applied to the first input terminal, and the first and the second differential input terminals.
In the test board of the fourteenth aspect, the first and the second signal transmission paths are formed in such a manner that the transmission path of the first test signal branches into two with the magnetic relay, the transistor or the power splitter.
The use of the magnetic relay or the MOS transistor allows easy control of the validity or invalidity of the first and the second signal transmission paths by the electric signal. On the other hand, the use of the power splitter allows impedance matching before and after the branch, which suppresses the occurrence of reflected noise of the signal applied to the first and the second input terminals.
In the test board of the fifteenth aspect, the first and the second delay means are formed of the axial cable determining the delay time according to its length, or the active delay element capable of setting the delay time through the predetermined setting operation.
The delay time can be relatively easily varied by varying the length of the axial cable or through the predetermined setting operation by the active delay element. This facilitates a variable setting of the first and the second signal propagation delay times.
An object of the present invention is to provide a semiconductor device and a test (DUT) board thereof achieving a high-precision timing verification test irrespective of the timing skew of the tester.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.